In recent years, non-volatile memories that are data-rewritable semiconductor devices are widely used. Memory may be classified into various types including, for example, a SLC (single-level cell) memory and a MLC (multi-level cell) memory. In SLC memory, a single memory cell stores a single bit; while in MLC memory, a single memory cell may store multiple bits.
In memory reading, an output current is obtained by applying a word line reference voltage to a gate of the memory cell and applying a bit line voltage to source/drain of the memory cell. The output current is compared with a reference current to determine the logic state of the memory cell.
FIG. 1 shows a reading distribution of a SLC memory, wherein the X-axis presents a threshold voltage (Vt) and the Y-axis presents quantity of cells. A moving algorithm is used to obtain a proper word line reference voltage. After reading the memory having a plurality of memory cells, it is checked that read data is correct or not and how many bits are error in read. In checking whether the read data is correct or not and how many bits are error in read, reading results of a reading operation on the memory cells are compared with an original data.
If the total number of bit 1 in the reading results is less than the total number of bit 1 in the original data, then the moving algorithm moves up the word line reference voltage, as shown in FIG. 2A. On the contrary, if the total number of bit 1 in the reading results is larger than the total number of bit 1 in the original data, then the moving algorithm moves down the word line reference voltage, as shown in FIG. 2B. In FIG. 2A and FIG. 2B, WL1˜WL3 refer to three different word line reference voltages.
After the word line reference voltage is moved, the reading operation on the memory cell and the error check operation are performed again. The movement of the word line reference voltage, the reading operation on the memory cell and the error check operation are repeated until the read data is correct.
However, there are some problems. Sometimes, the memory cells may have defect bits and tail bits and accordingly, the read distribution is divided into three distributions: main bits distribution, tail bits distribution and defect bits distribution, as shown in FIG. 3. Usually, almost memory cells are in main bits distribution. Some memory cells, which are tailed the main bits, are in tail bits distribution; and they may be caused by fast erasing, charge loss, charge gain and etc. Some memory cells, which are in the defect bits distribution, may be caused by process defects.
It is difficult in distinguishing defect bits and tail bits. If memory cells have both defect bits and tail bits, it needs more moving times in reading. FIG. 4 shows reading memory cells having both defect bits and tail bits in prior art. As shown in FIG. 4, in order to cover the defect bits (logic “0” for example), it needs to move the word line reference voltage 3 times (from WL1 to WL2, from WL2 to WL3 and from WL3 to WL4). Many word line reference voltage movements will lower reading speed. Further, the reading margin is small. In FIG. 4, RM 41 refers to reading margin in reading logic “1” while RM 43 refers to reading margin in reading logic “0”.
Secondly, generally, there are a lot of word lines in a memory. Different word lines may have different read distribution. A page is a sub-block in the word line, i.e. a word line has a lot of pages. FIG. 5 shows reading different pages in the same word line by the prior art. As shown in FIG. 5, in reading P (0) (the first page in the word line), it needs three times in moving the word line reference voltage; and in reading P (1) or other page in the same word line, the word line reference voltage is moved from WL1 to WL2 for reading the tail bits. Therefore, it wastes a lot of time to move the word line reference voltage in different pages of the same word line.
Third, in prior art, read speed in reading MLC memory is also slow. In MLC memory, the main bit distribution is “11”, “10”, “01” and “00”. Level 3 reading and level 1 reading are used in reading MLC low bit. Level 2 reading is used in reading MLC high bit. FIG. 6A shows reading a page in MLC memory array. As shown in FIG. 6A, it is assumed that there are both defect bits and tails bits in the “01” distribution in the page. In order to cover the both defect bits and tails bits in the “01” distribution, it may need 3 times in moving the word line reference voltage in level 3 reading. However, 3 times in moving the word line reference voltage in level 3 reading may cause not enough time in level 1 reading (if it needs 2 times in moving the word line reference voltage in level 1 reading). If the MLC memory reading is limited by read timing limit (read latency), it is preferred to waste as few moving times in level 3 reading and in level 1 reading as possible. But as shown in FIG. 6A, it wastes a lot of times in moving the word line reference voltage in level 3 reading and in level 1 reading. So the read speed in reading MLC memory is limited.
FIG. 6B shows reading pages P(0) and P(n) in MLC memory array, N being a natural number, P(0) being an initial page of a word line and P(N) being other page of the same word line. As shown in FIG. 6B, in reading the initial page P(0), it may need 3 times in moving the word line reference voltage in level 3 reading and 2 times in moving the word line reference voltage in level 1 reading, respectively; and in reading page P(N), it may still need 3 times in moving the word line reference voltage in level 3 reading and 2 times in moving the word line reference voltage in level 1 reading, respectively. Therefore, it needs a lot of moving times.